Integrated circuits which utilize differential bipolar current mode logic (CML) have different voltage ranges with respect to logic high and logic low voltage levels than CMOS technologies. Accordingly, the use of both bipolar and CMOS technologies in a single integrated circuit requires a conversion of current mode logic (CML) differential voltage levels to CMOS compatible voltage level converters or vice versa. For example, it is well known in the art that a typical CML circuit operates with a differential swing of two to three hundred millivolts. In contrast, a typical CMOS circuit operates according to a single ended voltage within a specified voltage range. For example, with a power supply voltage of 3.0 volts, a voltage of 2.5 V to 3.0 V represents a logic high voltage level and a voltage of 0 V to 0.5 V represents a logic low voltage level. As can be readily understood, the combination of CML and CMOS circuitry in a single integrated circuit requires a differential to single-ended conversion and a level conversion.
FIG. 1a illustrates the basic circuitry for a prior art CML to CMOS voltage converter. An incoming CML voltage signal is applied across terminals A and AN, with A representing the non-inverted voltage signal and AN representing the inverted voltage signal. The terminal A is coupled to the base of a first npn bipolar junction transistor QN1. The collector of the transistor QN1 is coupled to a first terminal of a resistor R10. A second terminal of the resistor R10 is coupled to a high voltage supply Vcc. The emitter of the transistor QN1 is coupled to the emitter of a second npn bipolar junction transistor QN2. The emitters of each of the transistors QN1 and QN2 are coupled to a low voltage supply Vss through a first current source I.sub.S1. Preferably, the current source I.sub.S1, is comprised of a NMOS transistor N100 which is driven by a biasing voltage, V.sub.BIAS, coupled to the gate of the NMOS transistor N100. The base of the transistor QN2 is coupled to the terminal AN, while the collector of the transistor QN2 is coupled to a first terminal of a resistor R20. A second terminal of the resistor R20 is coupled to the high voltage supply Vcc. The base of a third npn bipolar junction transistor QN3 is also coupled to the first terminal of the resistor R20 and to the collector of the transistor QN2. The collector of the transistor QN3 is coupled to the high voltage supply Vcc, while the emitter of the transistor QN3 is coupled to the source of a first PMOS transistor T10 and the source of a second PMOS transistor T20. The drain of the first PMOS transistor T10 is coupled to the gate of the first PMOS transistor T10 and the gate of a third PMOS transistor T30. The drain of the first PMOS transistor T10 is further coupled to the low voltage supply Vss, through a second current source, I.sub.S2. The second current source I.sub.2 is comprised of an NMOS transistor N200 which is driven by the biasing voltage, VBIAS, which is coupled to the gate of the NMOS transistor N200. The drain of the second PMOS transistor T20 is coupled to an output node B. The gate of the second PMOS transistor T20 is coupled to the gate of a fourth PMOS transistor T40 and the drain of the fourth PMOS transistor T40. The drain of the fourth PMOS transistor T40 is coupled to the low voltage supply Vss through a third current source, I.sub.S3. The third current source I.sub.3 is comprised of an NMOS transistor N300 which is driven by the biasing voltage V.sub.BIAS, coupled to the gate of the NMOS transistor N300. The source of the fourth PMOS transistor T40 is coupled to the emitter of a fourth npn bipolar junction transistor QN4. The collector of the transistor QN4 is coupled to the high voltage supply Vcc. The base of the transistor QN4 is coupled to the collector of the transistor QN1 and the first terminal of the resistor R10. The source of the third PMOS transistor T30 is also coupled to the emitter of the fourth bipolar junction transistor QN4. The drain of the third PMOS transistor T30 is coupled to the drain and the gate of a first NMOS transistor N10 and the gate of a second NMOS transistor N20. The source of the first NMOS transistor N10 and the source of the second NMOS transistor N20 are each coupled to the low voltage supply Vss. The drain of the second NMOS transistor N20 is coupled to the output node B. The output node B drives a CMOS buffer V.sub.10.
The internal circuitry of the CMOS buffer V.sub.10 is depicted in FIG. 1b. As shown in FIG. 1b, the CMOS buffer V.sub.10 includes a PMOS transistor P1 having a source connected to the high voltage supply Vcc, a gate coupled to the output node B and a drain coupled to an output node Q. The CMOS buffer V.sub.10 further includes an NMOS transistor N1 having a drain which is coupled to the output node Q. The gate of the NMOS transistor N1 is coupled to the output node B and the source of the NMOS transistor N1 is coupled to the low voltage supply Vss.
Referring again to FIG. 1a, when the differential voltage signal at the terminals A and AN is configured such that A is higher than AN, the transistor QN1 is turned on, while the transistor QN2 is off. In this state, an output voltage level measured at the output node B is switched toward the low voltage level Vss. The output voltage at the node B falls to very nearly the level of Vss when the transistor N20 sinks current out of the node B. As the voltage signal at the terminal A becomes inactive and the voltage signal at the terminal AN goes active, the output voltage at the output node B switches and begins to increase toward the high voltage level Vcc. However, due to the voltage drop associated with the bipolar junction transistors QN3, the voltage at the output node B will not reach the same voltage level as Vcc; but, rather, will actually only rise to the level of Vcc less one V.sub.BE voltage level of the transistor QN3 and the drain to source saturation voltage level of the transistor T20. Typically, this voltage may be as high as 0.8-1.0 volts, depending upon the operating conditions. Because the voltage at the output node B can fall to very nearly the level of Vss, but cannot rise to very nearly the level of Vcc, the voltage level at the output node B will not vary symmetrically with respect to the supply rails Vcc and Vss. This results in different rise and fall times for the voltage at the output Q of the CMOS buffer V.sub.10 because the input threshold of the CMOS buffer V.sub.10 is centered about 1/2Vcc.
Consider now the CMOS buffer of FIG. 1b. Ideally, when the NMOS transistor N1 is on, the PMOS transistor P1 should be off, and the voltage at the output Q will be driven low toward Vss. Conversely, when the PMOS transistor P1 is on, the NMOS transistor N1 should be off, and the voltage at the output Q will be driven high toward Vss. However, if the voltage at the node B is not driven high enough, the PMOS transistor P1 will not be completely turned off when the NMOS transistor N1 is on. In these circumstances, current will continue to flow through P1 to the output Q as current is drawn from the output Q through the NMOS transistor N1. Under these circumstances, the fall time required for the voltage level at the output Q to reach Vss will take longer than the rise time required for the voltage level at the output Q to reach Vcc. Accordingly, the voltage at the output Q will have an unsymmetrical duty cycle.
When such a prior art CML to CMOS converter is utilized for converting a clock signal from CML to CMOS, the converted clock signal will not have a constant duty cycle since the rise time and fall time will differ. This is undesirable in critical CMOS applications where a symmetric duty cycle is needed.
Additionally, it may be desirable to have both a CMOS output signal and its inverted complement, that are matched and track each other over process and temperature variations. In prior art CML to CMOS converters, the complement of the output voltage is often generated by using a CMOS inverter and simply inverting the output. One problem with such a method is the association of a delay with the inverter. In such cases, the complement will not be in synch with the uncomplemented output voltage; but, instead, will be delayed by a small fraction of time associated with the inverter. In many critical applications, such as the generation of CMOS compatible clocking signals, this delay in time is unacceptable. This problem has been overcome in the past by inverting the output voltage twice (in parallel with an inverter used for the complement) in order to obtain a new output voltage having the same frequency and period of the original output voltage.
FIG. 2 illustrates a prior art method for generating an inverted or complementary output signal. As shown, a CML signal is input to a CML to CMOS converter 500 at the input terminal I. A CMOS signal is output from the converter 500 at the output terminal OUT. The output terminal OUT is coupled to a first inverter X.sub.1 and a second inverter X.sub.2. The output from the first inverter X.sub.1 is input to a third inverter X.sub.3. The output from the second inverter X.sub.2 is the inverted or complementary output signal NOUT, while the output from the third inverter X.sub.3 is the original output signal. Each of the inverters X.sub.1, X.sub.2, and X.sub.3 has an associated timing delay, with the inverter X.sub.1 having a delay of T.sub.1, the inverter X.sub.2 having a delay of T.sub.2, and the inverter X.sub.3 having a delay of T.sub.3. As described above, in prior art configurations the inverters X.sub.1, X.sub.2, and X.sub.3 are each chosen such that the sum of the delays for the first and third inverters T.sub.1 +T.sub.3 is approximately equal to the delay of the second inverter T.sub.2. In this way, the output signal OUT and the inverted or complementary output signal are in synch. However, such circuitry is often complicated and difficult to design and the delays may vary under differing operating conditions such that obtaining optimized synchronization is extremely difficult. Delay matching involved adjusting the geometries of CMOS gate width and length to control delay of one signal with respect to another. Process variations, such as threshold voltage over temperature, do not make this an optimized solution for critical timing applications.
Accordingly, what is needed is an improved design which allows the converter to reach the desired high output voltage level required for CMOS circuitry so as to maintain a relatively constant duty cycle. What is further needed is a CML to CMOS converter which can output both the CMOS signal and its inverted complement, without any delay between the two voltage signals such that both signals are in synch without the need for complicated circuitry.